This title appears in the Scientific Report : 2014 

Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA
Kleines, Harald (Corresponding author)
Wustner, Peter / Drochner, Matthias / Ackens, Axel / Erven, Wilhelm / Kammerling, Peter / Ramm, Michael / van Waasen, Stefan
Zentralinstitut für Elektronik; ZEA-2
IEEE 2012
2012 IEEE-NPSS Real Time Conference (RT 2012), Berkeley (CA), 2012-06-09 - 2012-06-15
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In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.