Trellenkamp, S., Moers, J., van der Hart, A., Kordos, P., & Lüth, H. (2003). Patterning of 25nm wide Silicon Ridges for vertical Double-Gate MOSFETs. Bad Honnef: DPG.
Chicago Style CitationTrellenkamp, S., J. Moers, A. van der Hart, P. Kordos, andfavorite H. Lüth. Patterning of 25nm Wide Silicon Ridges for Vertical Double-Gate MOSFETs. Bad Honnef: DPG, 2003.
MLA CitationTrellenkamp, S., et al. Patterning of 25nm Wide Silicon Ridges for Vertical Double-Gate MOSFETs. Bad Honnef: DPG, 2003.
Warning: These citations may not always be 100% accurate.