This title appears in the Scientific Report :
2017
Please use the identifier:
http://dx.doi.org/10.1088/1748-0221/12/03/C03063 in citations.
First results of the front-end ASIC for the strip detector of the PANDA MVD
First results of the front-end ASIC for the strip detector of the PANDA MVD
PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with th...
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Personal Name(s): | Quagli, T. (Corresponding author) |
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Brinkmann, K.-T. / Calvo, D. / Pietro, V. Di / Lai, A. / Riccardi, A. / Ritman, J. / Rivetti, A. / Rolo, M. D. / Stockmanns, T. / Wheadon, R. / Zambanini, A. | |
Contributing Institute: |
Zentralinstitut für Elektronik; ZEA-2 Experimentelle Hadronstruktur; IKP-1 |
Published in: | Journal of Instrumentation, 12 (2017) 03, S. C03063 - C03063 |
Imprint: |
London
Inst. of Physics
2017
|
DOI: |
10.1088/1748-0221/12/03/C03063 |
Document Type: |
Journal Article |
Research Program: |
FAIR Detector technology and systems |
Publikationsportal JuSER |
PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed. |