Description: Hands-on Practical Hybrid Parallel Application Performance Engineering

This title appears in the Scientific Report : 2018

Hands-on Practical Hybrid Parallel Application Performance Engineering

This tutorial presents state-of-the-art performance tools for leading-edge HPC systems founded on the community-developed Score-P instrumentation and measurement infrastructure, demonstrating how they can be used for performance engineering of effective scientific applications based on standard MPI,...

Personal Name(s):	Feld, Christian
	Geimer, Markus / Shende, Sameer / Tschüter, Ronny
Contributing Institute:	Jülich Supercomputing Center; JSC
Imprint:	2018
Conference:	ISC High Performance '18, Frankfurt/Main (Germany), 2018-06-24 - 2018-06-28
Document Type:	Lecture
Research Program:	Computational Science and Mathematical Methods
Link:	OpenAccess OpenAccess
	Publikationsportal JuSER

Please use the identifier: http://hdl.handle.net/2128/19700 in citations.

This tutorial presents state-of-the-art performance tools for leading-edge HPC systems founded on the community-developed Score-P instrumentation and measurement infrastructure, demonstrating how they can be used for performance engineering of effective scientific applications based on standard MPI, OpenMP, hybrid combination of both, and increasingly common usage of accelerators. Parallel performance tools from the Virtual Institute – High Productivity Supercomputing (VI-HPS) are introduced and featured in hands-on exercises with Score-P, Scalasca, Vampir, and TAU. We present the complete workflow of performance engineering, including instrumentation, measurement (profiling and tracing, timing and PAPI hardware counters), data storage, analysis, tuning, and visualization. Emphasis is placed on how tools are used in combination for identifying performance problems and investigating optimization alternatives. Using their own notebook computers with a provided HPC Linux [http://www.hpclinux.org] OVA image containing all of the necessary tools (running within a virtual machine), participants will conduct exercises on the Stampede system at TACC where remote access to Intel Xeon Phi (KNL) nodes will be provided for the hands-on sessions. This will help to prepare participants to locate and diagnose performance bottlenecks in their own parallel programs.