VLSI-SoC: Design Trends [E-Book] : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers / edited by Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis.
This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed a...
Saved in:
Full text |
|
Personal Name(s): | Calimera, Andrea, editor |
Gaillardon, Pierre-Emmanuel, editor / Korgaonkar, Kunal, editor / Kvatinsky, Shahar, editor / Reis, Ricardo, editor | |
Edition: |
1st edition 2021. |
Imprint: |
Cham :
Springer,
2021
|
Physical Description: |
XVIII, 364 pages 209 illustrations, 139 illustrations in color (online resource) |
Note: |
englisch |
ISBN: |
9783030816414 |
DOI: |
10.1007/978-3-030-81641-4 |
Series Title: |
/* Depending on the record driver, $field may either be an array with
"name" and "number" keys or a flat string containing only the series
name. We should account for both cases to maximize compatibility. */?>
IFIP Advances in Information and Communication Technology ;
621 |
Subject (LOC): |
- Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22nm FDSOI
- A 125 pJ/b Mixed-Mode MCMC MIMO Detector with Relaxed DSP
- Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring
- Fully-Autonomous SoC Synthesis using Customizable Cell-Based Analog and Mixed-signal Circuits Generation
- Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform
- SAT-Based Mapping of Data-Flow Graph onto Coarse-Grained Reconfigurable Array
- Learning Based Timing Closure on Relative Timed Design
- Multilevel Signalling for High-Speed Chiplet-to-Chiplet Communication
- From Informal Specifications to an ABV Framework for Industrial Firmware Verification
- Modular Functional Testing: Targeting the Small Embedded Memories in GPUs
- RAT: A Lightweight Architecture Independent System-level Soft Error Mitigation Technique
- SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption
- 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs
- 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
- Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics
- A Technology Backward-Compatible Compilation Flow for Processing-In-Memory.