This title appears in the Scientific Report :
2023
Please use the identifier:
http://dx.doi.org/10.34734/FZJ-2023-03437 in citations.
Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV
Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV
In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the...
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Personal Name(s): | Nassyr, Stepan (Corresponding author) |
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Haghighi Mood, Kaveh / Herten, Andreas | |
Contributing Institute: |
Jülich Supercomputing Center; JSC |
Imprint: |
2023
|
DOI: |
10.34734/FZJ-2023-03437 |
Conference: | RISC-V Summit Europe 2023, Barcelona (Spain), 2023-06-05 - 2023-06-09 |
Document Type: |
Poster |
Research Program: |
Pilot using Independent Local & Open Technologies Doktorand ohne besondere Förderung Future Computing & Big Data Systems |
Link: |
Get full text OpenAccess OpenAccess |
Publikationsportal JuSER |
In this work, we introduce a tool that can generate compute kernels for different ISAs. The focus is on two Vector-Length-Agnostic (VLA) ISAs, ARM SVE and RISC-V RVV, in which the vector size is not fixed at compile time. The generator was applied to generate highly-optimized ARM SVE kernels for the A64FX processor. We use the same approach to generate RISC-V RVV 0.7.1 kernels for the Allwinner D1, a commercially available non-HPC RISC-V processor with support for a draft version of the RVV extension, as well as the FPGA SDV (RVV 0.7.1) of the in-development EUPILOT VEC accelerator and evaluate the performance |