This title appears in the Scientific Report :
2023
Please use the identifier:
http://dx.doi.org/10.1016/j.cpc.2022.108555 in citations.
Please use the identifier: http://dx.doi.org/10.34734/FZJ-2023-05489 in citations.
Portable CPU implementation of Wilson, Brillouin and Susskind fermions in lattice QCD
Portable CPU implementation of Wilson, Brillouin and Susskind fermions in lattice QCD
A modern Fortran implementation of three Dirac operators (Wilson, Brillouin, Susskind) in lattice QCD is presented, based on OpenMP shared-memory parallelization and SIMD pragmas.The main idea is to apply a Dirac operator to $N_v$ vectors simultaneously, to ease the memory bandwidth bottleneck.All i...
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Personal Name(s): | Durr, Stephan (Corresponding author) |
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Contributing Institute: |
Jülich Supercomputing Center; JSC |
Published in: | Computer physics communications, 282 (2023) S. 108555 - |
Imprint: |
Amsterdam
North Holland Publ. Co.
2023
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DOI: |
10.1016/j.cpc.2022.108555 |
DOI: |
10.34734/FZJ-2023-05489 |
Document Type: |
Journal Article |
Research Program: |
Fortschritte bei einer präzisen ab initio Bestimmung der Partonen-Struktur von Hadronen Domain-Specific Simulation & Data Life Cycle Labs (SDLs) and Research Groups |
Link: |
Published on 2022-09-26. Available in OpenAccess from 2024-09-26. |
Publikationsportal JuSER |
Please use the identifier: http://dx.doi.org/10.34734/FZJ-2023-05489 in citations.
A modern Fortran implementation of three Dirac operators (Wilson, Brillouin, Susskind) in lattice QCD is presented, based on OpenMP shared-memory parallelization and SIMD pragmas.The main idea is to apply a Dirac operator to $N_v$ vectors simultaneously, to ease the memory bandwidth bottleneck.All index computations are left to the compiler and maximum weight is given to portability and flexibility.The lattice volume, $N_x N_y N_z N_t$, the number of colors, $N_c$, and the number of right-hand sides, $N_v$, are parameters defined at compile time.Several memory layout options are compared.The code performs well on modern many-core architectures (480\,Gflop/s, 880\,Gflop/s, and 780\,Gflop/s with $N_v=12$for the three operators in single precision on a 72-core KNL processor, a $2 \times 24$-core Skylake node yields similar results).Explicit run-time tests with CG/BiCGstab inverters confirm that the memory layout is relevant for the KNL, but less so for the Skylake architecture.The ancillary code distribution contains all routines, including the single, double, and mixed precision Krylov space solvers, to render it self-contained and ready-to-use. |