This title appears in the Scientific Report :
2013
FE-I4 ATLAS Pixel Chip Design
FE-I4 ATLAS Pixel Chip Design
FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. It is designed in a 130 nm CMOS process and is based on an array of 80 by 336 pixels, each 50×250 μm2 fo...
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Personal Name(s): | Barbero, M. (Corresponding author) |
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Arutinov, D. / Hemperek, T. / Karagounis, M. / Kruth, Andre / Wermes, N. | |
Contributing Institute: |
Zentralinstitut für Elektronik; ZEA-2 |
Imprint: |
2009
|
Physical Description: |
1-10 |
Conference: | 18th International Workshop on Vertex Detectors and related techniques, Veluwe (Netherland), 13092009 - 19092009 |
Document Type: |
Contribution to a conference proceedings |
Research Program: |
ohne Topic |
Publikationsportal JuSER |
FE-I4 is the new ATLAS pixel chip developed for use in upgraded luminosity environments, in
the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of
Super-LHC. It is designed in a 130 nm CMOS process and is based on an array of 80 by 336
pixels, each 50×250 μm2 for an overall size of about 19×20 mm2. Each pixel consists of analog
and synthesized digital sections. The analog pixel section is designed for low power
consumption and compatibility to several sensor candidates. The digital architecture is based on
a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency
design, and provides a solution to record hits timewalk-free. A mixture of techniques is used for
yield enhancement. The chip periphery contains a control block, a command decoder and global
memory, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b
coder and a clock multiplier unit, which allows data transmission up to 160 Mb/s for the IBL. |