This title appears in the Scientific Report :
2011
Please use the identifier:
http://dx.doi.org/10.1109/TED.2011.2135355 in citations.
Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing
Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing
We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining e...
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Personal Name(s): | Smith, J.T. |
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Sandow, C. / Das, S. / Minamisawa, R.A. / Mantl, S. / Appenzeller, J. | |
Contributing Institute: |
Halbleiter-Nanoelektronik; PGI-9 JARA-FIT; JARA-FIT |
Published in: | IEEE Transactions on Electron Devices, 58 (2011) S. 1822 - 1829 |
Imprint: |
2011
|
Physical Description: |
1822 - 1829 |
DOI: |
10.1109/TED.2011.2135355 |
Document Type: |
Journal Article |
Research Program: |
Grundlagen für zukünftige Informationstechnologien |
Series Title: |
IEEE Transactions on Electron Devices
58 |
Subject (ZB): | |
Publikationsportal JuSER |
We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laser annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggressively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures. |