This title appears in the Scientific Report :
2015
Please use the identifier:
http://dx.doi.org/10.1007/978-3-319-17248-4_2 in citations.
Performance Evaluation of Scientific Applications on POWER8
Performance Evaluation of Scientific Applications on POWER8
With POWER8 a new generation of POWER processors became available. This architecture features a moderate number of cores, each of which expose a high amount of instruction-level as well as thread-level parallelism. The high-performance processing capabilities are integrated with a rich memory hierar...
Saved in:
Personal Name(s): | Adinets, Andrey |
---|---|
Baumeister, Paul F. (Corresponding Author) / Böttiger, Hans / Hater, Thorsten / Maurer, Thilo / Pleiter, Dirk / Schenck, Wolfram / Schifano, Sebastiano Fabio | |
Contributing Institute: |
Jülich Supercomputing Center; JSC |
Published in: |
High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation / ; Cham : Springer International Publishing, 2015, Chapter 2 ; ISSN: 0302-9743=1611-3349 ; ISBN: 978-3-319-17247-7=978-3-319-17248-4 ; doi:10.1007/978-3-319-17248-4 |
Imprint: |
Cham
Springer International Publishing
2015
|
Physical Description: |
24 - 45 |
ISBN: |
978-3-319-17247-7 (print) 978-3-319-17248-4 (electronic) |
DOI: |
10.1007/978-3-319-17248-4_2 |
Conference: | 5th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (held as part of SC14), New Orleans, LA (USA), 2014-11-16 - 2014-11-16 |
Document Type: |
Contribution to a book Contribution to a conference proceedings |
Research Program: |
SimLab Neuroscience Supercomputer Facility |
Series Title: |
Lecture Notes in Computer Science
8966 |
Publikationsportal JuSER |
With POWER8 a new generation of POWER processors became available. This architecture features a moderate number of cores, each of which expose a high amount of instruction-level as well as thread-level parallelism. The high-performance processing capabilities are integrated with a rich memory hierarchy providing high bandwidth through a large set of memory chips. For a set of applications with significantly different performance signatures we explore efficient use of this processor architecture. |