This title appears in the Scientific Report :
2022
Please use the identifier:
http://hdl.handle.net/2128/31394 in citations.
Please use the identifier: http://dx.doi.org/10.1088/2634-4386/ac6d04 in citations.
Reliability aspects of binary vector-matrix-multiplications using ReRAM devices
Reliability aspects of binary vector-matrix-multiplications using ReRAM devices
Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive...
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Personal Name(s): | Bengel, Christopher (Corresponding author) |
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Mohr, Johannes / Wiefels, Stefan / Singh, Abhairaj / Gebregiorgis, Anteneh / Bishnoi, Rajendra / Hamdioui, Said / Waser, Rainer / Wouters, Dirk / Menzel, Stephan | |
Contributing Institute: |
Elektronische Materialien; PGI-7 JARA-FIT; JARA-FIT JARA Institut Green IT; PGI-10 |
Published in: | Neuromorphic computing and engineering, 2 (2022) 3, S. 034001 - |
Imprint: |
Bristol
IOP Publishing Ltd.
2022
|
DOI: |
10.1088/2634-4386/ac6d04 |
Document Type: |
Journal Article |
Research Program: |
Computation-in-memory architecture based on resistive devices Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - Verbundprojekt: Neuro-inspirierte Technologien der künstlichen Intelligenz für die Elektronik der Zukunft - NEUROTEC II - Memristive Materials and Devices |
Link: |
OpenAccess |
Publikationsportal JuSER |
Please use the identifier: http://dx.doi.org/10.1088/2634-4386/ac6d04 in citations.
Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm's law and Kirchhoff's law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction. |