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1

Journal Article

Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs

Blaeser, Sebastian
2016

IEEE transactions on electron devices, 63 (2016) 11, S. 4173 - 4178

2

Contribution to a book
Contribution to a conference proceedings

Current mirrors with strained Si single nanowire gate all around Schottky barrier MOSFETs

Narimani, Keyvan
2016

3

Contribution to a book

(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics

Zhao, Qing-Tai
2015

4

Contribution to a conference proceedings

Novel SiGe/Si line tunneling TFET with high Ion at low Vdd and constant SS

Blaeser, S.
2015

5

Journal Article

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Zhao, Qing-Tai
2015

IEEE journal of the Electron Devices Society, 3 (2015) 3, S. 103 - 114

OpenAccess OpenAccess

6

Contribution to a conference proceedings

Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V

Richter, Simon
2014

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