Computer architecture : a quantitative approach / John L. Hennessy ; David A. Patterson
Saved in:
Table of Contents |
|
Personal Name(s): | Hennessy, John L. |
Patterson, David A. | |
Edition: |
4th ed. |
Imprint: |
Amsterdam :
Elsevier Morgan Kaufmann Publ.,
2007
|
Physical Description: |
Getr. Pag. |
Note: |
englisch |
ISBN: |
9870123704900 9780123704900 0123704901 |
Keywords: |
fundamentals of computer design instruction set principles and dynamic exploitations memory hierarchy design and storage systems multiprocessors and thread level parallelism interconnection networks and clusters pipelining |
Subject (ZB): | |
Classification: |
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---|---|---|---|
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005 | 20070307000000.0 | ||
008 | r2007 | ||
020 | |a 9870123704900 | ||
020 | |a 0123704901 | ||
035 | |a (Sirsi) a172614 | ||
041 | |a eng | ||
084 | 0 | |a DGAA - Computer architectures | |
084 | 0 | |a 011 - Simulation Science (advanced reading) | |
245 | 0 | 0 | |a Computer architecture : |b a quantitative approach / |c John L. Hennessy ; David A. Patterson |
250 | |a 4th ed. | ||
260 | |a Amsterdam : |b Elsevier Morgan Kaufmann Publ., |c 2007 | ||
300 | |a Getr. Pag. | ||
500 | |a englisch | ||
596 | |a 1 34 | ||
650 | 4 | |a computer architecture | |
653 | |a fundamentals of computer design | ||
653 | |a instruction set principles and dynamic exploitations | ||
653 | |a memory hierarchy design and storage systems | ||
653 | |a multiprocessors and thread level parallelism | ||
653 | |a interconnection networks and clusters | ||
653 | |a pipelining | ||
700 | 1 | |a Hennessy, John L. | |
700 | 1 | |a Patterson, David A. | |
856 | |u http://wwwzb.fz-juelich.de/contentenrichment/inhaltsverzeichnisse/bis2009/ISBN-0-12-370490-1.pdf |z Inhaltsverzeichnis | ||
900 | |a B 086550'04' | ||
908 | |a Lehrbuch | ||
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