A Cryogenic Voltage Regulator with Integrated Voltage Reference in 22 nm FDSOI Technology
A Cryogenic Voltage Regulator with Integrated Voltage Reference in 22 nm FDSOI Technology
High performance ICs (Integrated Circuits) operating at cryogenic temperatures will be a fundamental part of future quantum computers, providing precise manipulation of a large number of qubits [1], [2]. However, these ICs will need regulated and stable supply voltages in situ for optimum operation...
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Personal Name(s): | Cabrera Galicia, Alfonso Rafael (Corresponding author) |
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Ashok, Arun / Vliex, Patrick / Kruth, Andre / Zambanini, Andre / van Waasen, Stefan | |
Contributing Institute: |
Zentralinstitut für Elektronik; ZEA-2 |
Imprint: |
IEEE
2023
|
Physical Description: |
304-308 |
ISBN: |
979-8-3503-8119-1 |
DOI: |
10.1109/APCCAS60141.2023.00075 |
DOI: |
10.34734/FZJ-2024-03293 |
DOI: |
10.1109/APCCAS60141.2023 |
Conference: | 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Hyderabad (India), 2023-11-19 - 2023-11-22 |
Document Type: |
Contribution to a book Contribution to a conference proceedings |
Research Program: |
Quantum-Computer Control Systems and Cryoelectronics |
Subject (ZB): | |
Link: |
OpenAccess |
Publikationsportal JuSER |
Please use the identifier: http://dx.doi.org/10.34734/FZJ-2024-03293 in citations.
Please use the identifier: http://dx.doi.org/10.1109/APCCAS60141.2023 in citations.
High performance ICs (Integrated Circuits) operating at cryogenic temperatures will be a fundamental part of future quantum computers, providing precise manipulation of a large number of qubits [1], [2]. However, these ICs will need regulated and stable supply voltages in situ for optimum operation due to their mixed signal nature [3], [4]. Accordingly, this paper presents the design and cryogenic electrical characterization of a voltage regulator with an integrated voltage reference. Together, the circuits can generate a regulated voltage of 1.15 V with up to 10 mA of output current capability at 6 K. The investigated circuits exploit two cryogenic MOS transistor phenomena, the threshold voltage (Vth) saturation and the transconductance (gm) increase. The circuits were developed in 22 nm FDSOI technology. |